Microelectronic capacitors are becoming increasingly important in microelectronic devices. For example, microelectronic capacitors are widely used in integrated circuit memory devices, such as dynamic random access memory (DRAM) devices. Moreover, as the integration density of memory devices continues to increase, memory devices having larger per-unit area capacitance are often needed to compensate for the reduced capacitance size. Thus, much research has been performed to obtain larger capacitance in submicron devices.
As is well known to those having skill in the art, a capacitor includes a pair of spaced-apart conductive electrodes with a dielectric therebetween. Thus, efforts in obtaining larger capacitance in microelectronic capacitors have generally concentrated on three aspects: reduction of the dielectric thickness, increasing the effective area of the capacitor, and using dielectric material having a high dielectric constant.
Unfortunately, a reduction in the dielectric thickness may be limited by the physical nature of the dielectric material. In particular, although the capacitance generally increases as the thickness of the dielectric is reduced, reduction in thickness beyond a certain limit generally raises the leakage current due to dielectric breakdown. Accordingly, there is generally a limit on how thin the dielectric can be made.
Efforts have also been made to increase the effective area of the capacitor by forming three-dimensional capacitor structures, such as trench, stack or cylinder-type capacitors or combinations thereof. Unfortunately, these three-dimensional geometrical structures tend to complicate the manufacturing process.
In view of the above, efforts have also concentrated in increasing the dielectric constant of the dielectric. A dielectric having a high dielectric constant may provide sufficient capacitance without requiring a complicated capacitor structure or endangering dielectric breakdown of the dielectric.
Many materials have been investigated for their high dielectric constant. For example, tantalum pentoxide (Ta.sub.2 O.sub.5), titanium strontium trioxide (SrTiO.sub.3) and titanium strontium barium trioxide ((BaSr)TiO.sub.3) have all been investigated. Although titanium strontium trioxide and titanium strontium barium trioxide may have a dielectric constant as high as about 300-600, it has been found difficult to control the composition thereof and to bond these dielectrics to other materials. Thus, they are not widely used.
On the other hand, tantalum pentoxide has been widely used, but has produced problems of unacceptably large leakage current in thin films thereof.
FIGS. 1A-1D are cross-sectional views illustrating a conventional microelectronic capacitor including a tantalum pentoxide dielectric, during intermediate fabrication steps. The completed microelectronic capacitor is shown in FIG. 1D. As shown in FIG. 1D, the capacitor is formed on a semiconductor substrate 10. Field oxide films 12 may be included. A source area 14 to which the capacitor is connected, may also be included. An insulating layer 16 separates the capacitor from the semiconductor substrate 10. A conductive plug 18 connects the capacitor to the source area 14.
The capacitor itself is formed of a conductive layer 20', a tantalum pentoxide film 22 thereon, and a second conductive electrode 24 thereon. When the capacitor is used in an integrated circuit memory device, the first conductive electrode 20' is often referred to as a storage electrode and the second conductive electrode 24 is often referred to as a plate electrode.
Referring again to FIGS. 1A-1D, a method for fabricating a conventional integrated circuit capacitor will now be described. As shown in FIG. 1A, a field oxide film 12 and a source area 14 are formed in a silicon substrate 10. Insulating material 16 is deposited on the substrate 10. A contact hole 17 is patterned in the insulating layer 16 to expose the source area 14. A conductive plug 18 is then formed in the hole 17, for example by depositing impurity doped polysilicon and then etching the impurity doped silicon layer from the surface of the insulating layer 16, so that the conductive plug 18 remains.
Referring now to FIG. 1B, a first conductive layer 20 is formed on the semiconductor substrate 10 over the conductive plug 18. The first conductive layer may be formed of impurity doped polysilicon, WN, TiN, Pt, WSi or combinations of these and/or other materials.
Then, referring to FIG. 1C, a storage electrode 20' is formed by patterning the conductive layer 20 using photolithography or other known processes, so as to expose a portion of insulating layer 16. A tantalum pentoxide film 22 is then formed over the semiconductor substrate 10. The tantalum pentoxide film 22 is preferably formed using penta-ethoxy-tantalum, Ta(OC.sub.2 H.sub.5).sub.5, as a raw material using sputtering, chemical vapor deposition, liquid source chemical vapor deposition, photo chemical vapor deposition, sol-gel methods or other conventional techniques.
Finally, as shown in FIG. 1D, a plate electrode 24 is formed on the tantalum pentoxide film. The plate electrode 24 may be formed of impurity doped polysilicon, WN, TiN, Pt, WSi or combinations of these and/or other materials.
Unfortunately, it has been found that in the dielectric film formed of tantalum pentoxide as described above, leakage current may be generated due to oxygen vacancies inside the tantalum pentoxide. In particular, when a capacitor having a tantalum pentoxide dielectric is heat treated in subsequent steps, oxygen atoms included in the dielectric film may be activated by the heat energy which is applied to the capacitor. The activated oxygen atoms tend to migrate into the electrode materials of the capacitor. Leakage currents are thereby produced. In other words, when the oxygen atoms become activated in the tantalum pentoxide thin film, oxygen vacancies occur which generate a leakage current.
It is known to reduce leakage current of the tantalum pentoxide thin film by annealing on the tantalum pentoxide film. An annealing method is described in a publication by Shinriki et al. entitled "UV-O.sub.3 DRY-O.sub.3 : Two-Step Annealed Chemical Vapor Deposited Ta.sub.2 O.sub.5 Films for Storage Dielectrics of 64-Mb DRAM's", IEEE, Vol. 38, No. 3, March 1991, pp. 455-462, the disclosure of which is hereby incorporated herein by reference.
The above-described two-step method first exposes the tantalum pentoxide to ultraviolet radiation and ozone. Then, the tantalum pentoxide is exposed to a dry oxygen treatment. The ultraviolet-ozone annealing treatment cures defects such as the oxygen vacancies. That is, the excited oxygen atoms which are generated from decomposition of ozone (O.sub.3) by ultraviolet rays (UV) are absorbed through the surface of the tantalum pentoxide film and diffused into the film, thereby filling the oxygen vacancies. The dry-oxygen annealing treatment cures defects, which are referred to as "weak spots", and reduces the density of carbon which is generated during the thermal decomposition of penta-ethoxy-tantalum which is used as the raw material for forming the tantalum pentoxide film.
Unfortunately, it has been found that the UV-O.sub.3 annealing treatment described in the above-cited publication has only a limited effect in minimizing the leakage current of the tantalum pentoxide film. In particular, as the thickness of the tantalum pentoxide film increases, the UV-O.sub.3 annealing treatment may become increasingly ineffective in filling oxygen vacancies. Accordingly, methods of forming high quality tantalum pentoxide films with reduced oxygen vacancies, are desirable.